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| 0 R XCR3128XL 128 Macrocell CPLD 0 14 DS016 (v2.4) November 11, 2004 Product Specification Features * * * * * Low power 3.3V 128 macrocell CPLD 6.0 ns pin-to-pin logic delays System frequencies up to 175 MHz 128 macrocells with 3,000 usable gates Available in small footprint packages - 144-pin TQFP (108 user I/O pins) - 144-ball CS BGA (108 user I/O) - 100-pin VQFP (84 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero PowerTM (FZP) CMOS design technology - 3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O) Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 available clocks per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for additional I/O 2.7V to 3.6V supply voltage at industrial temperature range Programmable slew rate control per output Security bit prevents unauthorized access Refer to XPLA3 family data sheet (DS012) for architecture description Description The XCR3128XL is a 3.3V 128 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of eight function blocks provide 3,000 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 175 MHz. TotalCMOS Design Technique for Fast Zero Power Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 or Figure 2 and Table 1or Table 2 showing the ICC vs. Frequency of the XCR3128XL TotalCMOS CPLD (data taken with eight resetable up/down, 16-bit counters at 3.3V, 25C). 80 70 60 * * Typical ICC (mA) 50 40 30 20 10 0 0 20 40 60 80 100 120 140 160 DS016_01_120902 * * * * * * Frequency (MHz) Figure 1: Typical ICC vs. Frequency at VCC = 3.3V, 25C Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25C Frequency (MHz) Typical ICC (mA) 0 0.02 1 0.5 5 2.48 10 4.97 20 9.89 40 19.7 60 29.5 80 39.1 100 48.7 120 58.0 140 67.3 160 76.8 (c) 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS016 (v2.4) November 11, 2004 Product Specification www.xilinx.com 1-800-255-7778 1 XCR3128XL 128 Macrocell CPLD R DC Electrical Characteristics Over Recommended Operating Conditions(1) Symbol VOH(2) Parameter Output High voltage Test Conditions VCC = 3.0V to 3.6V, IOH = -8 mA VCC = 2.7V to 3.0V, IOH = -8 mA IOH = -500 A VOL IIL IIH ICCSB ICC CIN CCLK CI/O Output Low voltage for 3.3V outputs Input leakage current I/O High-Z leakage current Standby current Dynamic current(4,5) Input pin I/O pin capacitance(6) capacitance(6) IOL = 8 mA VIN = GND or VCC to 5.5V VIN = GND or VCC to 5.5V VCC = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz Clock input Min. 2.4 2.0 90% VCC(3) -10 -10 Max. 0.4 10 10 100 1 30 8 12 10 Unit V V V V A A A mA mA pF pF pF capacitance(6) Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating conditions. 2. See Figure 2 for output drive characteristics of the XPLA3 family. 3. This parameter guaranteed by design and characterization, not by testing. 4. See Table 1, Figure 1 for typical values. 5. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 6. Typical values, not tested. 100 90 80 70 60 IOL (3.3V) mA 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH (2.7V) IOH (3.3V) Volts DS012_10_031802 Figure 2: Typical I/V Curve for the XPLA3 Family, 25C 2 www.xilinx.com 1-800-255-7778 DS016 (v2.4) November 11, 2004 Product Specification R XCR3128XL 128 Macrocell CPLD AC Electrical Characteristics Over Recommended Operating Conditions(1,2) -6 Symbol TPD1 TPD2 TCO TSUF TSU1 TSU2 TH (4) (4) (4) -7 Max. 5.5 6.0 4.0 20 20 175 100 100 7.5 7.5 7.0 8.0 3.0 4.3 4.8 0 3.0 5.0 Min. Max. 7.0 7.5 5.0 20 20 119 100 100 9.3 9.3 8.3 9.3 Min. 3.0 5.4 6.3 0 4.0 6.0 - -10 Max. 9.1 10.0 6.5 20 20 95 100 100 11.2 11.2 10.7 11.2 Unit ns ns ns ns ns ns ns ns ns ns ns MHz s s ns ns ns ns Parameter Propagation delay time (single p-term) Propagation delay time (OR array)(3) Clock to output (global synchronous pin clock) Setup time (fast input register) Setup time (single p-term) Setup time (OR array) Hold time Global Clock pulse width (High or Low) P-term clock pulse width Input rise time Input fall time Min. 2.5 3.5 4.0 0 2.5 4.0 - TWLH TR(4) TL (4) TPLH(4) fSYSTEM TINIT (4) (4) (4) (4) (4) Maximum system frequency Configuration time(5) ISP initialization time P-term OE to output enabled P-term OE to output disabled(6) P-term clock to output P-term set/reset to output valid TCONFIG TPOE TPOD TPCO(4) TPAO(4) Notes: 1. Specifications measured with one output switching. 2. See XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 6 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 9 mA at 3.6V. 6. Output CL = 5 pF. Soldering Temperature Symbol TSOL Parameter Maximum Soldering temperature (10s @ 1/16in. = 1.5mm) Min. Max. 220 Units C Internal Timing Parameters(1,2) -6 Symbol Buffer Delays TIN TFIN TGCK TOUT TEN Input buffer delay Fast Input buffer delay Global Clock buffer delay Output buffer delay Output buffer enable/disable delay 1.3 2.3 0.8 2.2 4.2 1.6 3.0 1.0 2.7 5.0 2.2 3.1 1.3 3.6 5.7 ns ns ns ns ns Parameter Min.(3) Max.(3) Min. -7 Max. Min. -10 Max. Unit Internal Register and Combinatorial Delays DS016 (v2.4) November 11, 2004 Product Specification www.xilinx.com 1-800-255-7778 3 XCR3128XL 128 Macrocell CPLD R -6 Symbol TLDI TSUI THI TECSU TECHO TCOI TAOI TRAI TPTCK TLOGI1 TLOGI2 TF TLOGI3 TUDA TSLEW Parameter Latch transparent delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to putput delay Register async. S/R to output delay Register async. recovery Product term clock delay Internal logic delay (single p-term) Internal logic delay (PLA OR term) Min.(3) 1.0 0.3 2.0 3.0 Max.(3) 1.3 1.0 2.5 4.0 2.5 2.0 2.5 Min. 1.0 0.5 2.5 4.5 - -7 Max. 1.6 1.3 2.3 5.0 2.7 2.7 3.2 Min. 1.2 0.7 3.0 5.5 - -10 Max. 2.0 1.6 2.1 6.0 3.3 3.3 4.2 Unit ns ns ns ns ns ns ns ns ns ns ns Feedback Delays ZIA delay 1.2 2.9 3.5 ns Time Adders Fold-back NAND delay Universal delay Slew rate limited delay 2.0 1.7 4.0 2.5 2.2 5.0 3.0 2.7 6.0 ns ns ns Notes: 1. These parameters guaranteed by design and/or characterization, not testing. 2. See XPLA family data sheet (DS012) for timing model. 3. Contact Xilinx for update on advance specification. 4 www.xilinx.com 1-800-255-7778 DS016 (v2.4) November 11, 2004 Product Specification R XCR3128XL 128 Macrocell CPLD Switching Characteristics VCC S1 Component R1 R2 C1 VOUT R2 C1 Values 390 390 35 pF R1 VIN Measurement TPOE (High) TPOE (Low) TP S1 Open Closed Closed S2 Closed Open Closed S2 Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH - 300 mV. DS016_03_102401 Figure 3: AC Load Circuit 6.0 5.8 +3.0V 90% 10% 5.6 ns 5.4 5.2 5.0 4.8 1 2 4 8 16 Number of Adjacent Outputs Switching DS016_04a_120902 0V TR 1.5 ns TL 1.5 ns Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. DS016_05_042800 Figure 5: Voltage Waveform Figure 4: Derating Curve for TPD2 DS016 (v2.4) November 11, 2004 Product Specification www.xilinx.com 1-800-255-7778 5 XCR3128XL 128 Macrocell CPLD R Pin Descriptions Table 2: XCR3128XL User I/O Pins VQ100 Total User I/O Pins 84 CS144 108 TQ144 108 Table 3: XCR3128XL I/O Pins (Continued) Function Block Macrocell 3 3 3 3 CS144 B12 D11(1) D12 D13 E10 E11 E12 E13 F10 F12 F13 G10 G11 A13 A12 B11 A11 D10 C10 B10 D9 C9 B9 A9 D8 C8 TQ144 106 104(1) 102 101 100 99 98 97 96 94 93 92 91 107 109 110 111 112 113 114 116 117 118 119 120 121 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 VQ100 62(1) 61 60 58 57 56 55 54 53 52 40 41 42 44 45 46 47 48 49 50 2 1 100 99 98 CS144 G13 G12(1) H13 H12 H11 J13 J12 J11 J10 K13 K12 K11 K10 M8 L8 K8 N9 L9 K9 N10 M10 L10 N11 M11 L11 M12 A1 A2 C3 B3 A3 TQ144 90 89(1) 88 87 86 84 83 82 81 80 79 78 77 60 61 62 63 65 66 67 68 69 70 71 72 74 1 143 142 141 140 Table 3: XCR3128XL I/O Pins Function Block Macrocell 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VQ100 73(1) 72 71 70 69 68 67 65 64 63 75 76 77 78 79 80 81 83 84 85 - 6 www.xilinx.com 1-800-255-7778 DS016 (v2.4) November 11, 2004 Product Specification R XCR3128XL 128 Macrocell CPLD Table 3: XCR3128XL I/O Pins (Continued) TQ144 139 138 137 136 134 133 132 131 2 4(1) 5 6 7 8 9 10 11 12 14 15 16 56 55 54 53 46 45 44 Function Block Macrocell 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Notes: 1. JTAG pins Table 3: XCR3128XL I/O Pins (Continued) Function Block Macrocell 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 VQ100 97 96 94 93 92 4(1) 5 6 7 8 9 10 12 13 14 37 36 35 33 32 31 CS144 C4 B4 A4 D5 B5 A5 D6 C6 B1 D2(1) D1 E4 E3 E2 E1 F4 F3 F2 G2 G1 G3 N7 M7 N6 M6 M5 L5 K5 - VQ100 30 29 28 27 15(1) 16 17 19 20 21 22 23 24 25 - CS144 N4 M4 L4 K4 N3 M3 H1 H2(1) H3 H4 J1 J3 J4 K1 K2 K3 L1 M2 N1 TQ144 42 41 40 39 38 37 18 20(1) 21 22 23 25 26 27 28 29 30 31 32 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DS016 (v2.4) November 11, 2004 Product Specification www.xilinx.com 1-800-255-7778 7 XCR3128XL 128 Macrocell CPLD R Table 4: XCR3128XL Global, JTAG, Port Enable, Power, and No Connect Pins Pin Type IN0 / CLK0 IN1 / CLK1 IN2 / CLK2 IN3 / CLK3 TCK TDI TDO TMS PORT_EN Vcc VQ100 90 89 88 87 62 4 73 15 11(1) CS144 D7 C7 A7 B7 G12 D2 D11 H2 F1(1) TQ144 128 127 126 125 89 4 104 20 13(1) 24, 50, 51, 58, 73, 76, 95, 115, 123, 130, 144 Table 4: XCR3128XL Global, JTAG, Port Enable, Power, and No Connect Pins Pin Type GND VQ100 26, 38, 43, 59, 74, 86, 95 CS144 TQ144 3, 17, 33, A6, A8, C5, 52, 57, 59, C13, D3, G4, H10, 64, 85, 105, 124, 129, L6, L7, M9, 135 N2, N8 B13, C1, C2, C11, C12, L2, L3, L12, M1, M13, N13 19, 34, 35, 36, 43, 47, 48, 49, 75, 103, 108, 122 No Connects - 3, 18, 34, A10, B2, B6, 39, 51, 66, B8, D4, F11, 82, 91 J2, K6, K7, L13, N5, N12 Notes: 1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for full explanation. 8 www.xilinx.com 1-800-255-7778 DS016 (v2.4) November 11, 2004 Product Specification R XCR3128XL 128 Macrocell CPLD Device Part Marking and Ordering Combination Information R Device Type Package Speed Operating Range XCRxxxxXL TQ144 7C This line not related to device part number 1 Sample package with part marking. Device Ordering and Part Marking Number XCR3128XL-6VQ100C XCR3128XL-6CS144C XCR3128XL-6TQ144C XCR3128XL-7VQ100C XCR3128XL-7CS144C XCR3128XL-7TQ144C XCR3128XL-7VQ100I XCR3128XL-7CS144I XCR3128XL-7TQ144I XCR3128XL-10VQ100C XCR3128XL-10CS144C XCR3128XL-10TQ144C XCR3128XL-10VQ100I XCR3128XL-10CS144I XCR3128XL-10TQ144I Speed (pin-to-pin delay) 6 ns 6 ns 6 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns Pkg. Symbol VQ100 CS144 TQ144 VQ100 CS144 TQ144 VQ100 CS144 TQ144 VQ100 CS144 TQ144 VQ100 CS144 TQ144 No. of Pins 100 144 144 100 144 144 100 144 144 100 144 144 100 144 144 Package Type Very Thin Quad Flat Package (VQFP) Chip Scale Package (CSP) Thin Quad Flat Pack (TQFP) Very Thin Quad Flat Package (VQFP) Chip Scale Package (CSP) Thin Quad Flat Pack (TQFP) Very Thin Quad Flat Package (VQFP) Chip Scale Package (CSP) Thin Quad Flat Pack (TQFP) Very Thin Quad Flat Package (VQFP) Chip Scale Package (CSP) Thin Quad Flat Pack (TQFP) Very Thin Quad Flat Package (VQFP) Chip Scale Package (CSP) Thin Quad Flat Pack (TQFP) Operating Range(1) C C C C C C I I I C C C I I I Notes: 1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = -40 to +85C Additional Information CoolRunner XPLA3 Datasheets and Application Notes Device Packages DS016 (v2.4) November 11, 2004 Product Specification www.xilinx.com 1-800-255-7778 9 XCR3128XL 128 Macrocell CPLD R Revision History The following table shows the revision history for this document. Date 04/07/00 05/03/00 11/20/00 12/08/00 01/17/01 04/11/01 04/19/01 08/10/01 01/08/02 Version 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Initial Xilinx release. Minor updates and added Boundary Scan to pinout table. Updated pinout tables; corrected note in Table 4 to read: "port enable pin is brought High". Updated pinout tables. Removed Timing Model. Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed VOH spec. Updated Typical I/V curve, Figure 2: added voltage levels. Moved Figure 1 and Table 1 to first page. Changed VQ144 to VQ100 in Table 2. Updated TSUF and TFIN spec to match software timing. Added single p-term setup time (TSU1) to AC Table, renamed TSU to TSU2 for setup time through the OR array. Added TINIT spec. Updated TCONFIG spec. Updated THI spec to correct a typo. Updated AC Load Circuit diagram to more closely resemble true test conditions, added note for TPOD delay measurement. Updated product availability and AC/DC parameters for -6 Commercial and -7 Industrial devices. Updated TPCO (added TPTCK), TCONFIG, TINIT, TF. Updated ICC vs. Frequency Curve for -6 device; updated system frequency to 175 MHz; removed Advance Information from -6 device; updated Derating Curve for -6 device. Updated Ordering Information format. Updated test conditions for IIL and IIH. Updated Package Device Marking Pin 1 orientation. Added soldering temperature. Added links to application notes and data sheets. Updated the following specifications based on characterization of product after move to UMC fabrication for all family members: VOH, TLOGI3. Deleted derating curve for TPD2 for MOSIV fabricated material. Moved from Preliminary Product Specification to Product Specification. Revision 01/27/03 1.9 07/15/03 08/21/03 02/13/04 07/09/04 2.0 2.1 2.2 2.3 11/11/04 2.4 10 www.xilinx.com 1-800-255-7778 DS016 (v2.4) November 11, 2004 Product Specification |
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